The present invention relates generally to semiconductor devices and methods of manufacture, and more particularly, to semiconductor devices and methods of manufacture including a trenched gate.
Conventional Metal Oxide Semiconductor (MOS) transistors for use in semiconductor devices are typically constructed with the gate being formed on a top surface of the semiconductor substrate. FIG. 1 is a cross-sectional view of a cell structure of a conventional MOS transistor 100 including a substrate 102 of a semiconductor crystal such as silicon. The transistor 100 also includes a channel region 104, a source region 106, a drain region 108 a gate dielectric layer 110, and a gate electrode 112. As shown in FIG. 1, the gate dielectric layer 110 and the gate electrode layer 112 are disposed on a top surface of the substrate 102.
As semiconductor devices and integrated circuits are scaled down in size demands for the efficient use of space have increased. Heretofore, conventional MOS circuits have utilized a device structure in which the transistor gate is formed on a top surface of the silicon substrate as shown in FIG. 1. However, this type of device structure is limited in the degree to which active devices can be made smaller in order to improve packing density and performance.
In accordance with the present invention a semiconductor device is fabricated to include a trenched polysilicon gate which is formed in a trench of a semiconductor substrate. The trenched polysilicon gate structure improves the overall topography of the structure for better process control and improved manufacturability. The trenched polysilicon gate structure of the present invention also advantageously improves the device packing density and scaleability by reducing the lateral diffusion of the source and drain regions under the trenched polysilicon gate. This invention also minimizes the process variations of overlaps between the trenched polysilicon gate and the source and drain regions.
In one embodiment of the present invention a device structure for an MOS circuit includes a trenched polysilicon rate. The trenched polysilicon gate is formed in a trench etched into the semiconductor substrate. The device structure further includes a source region a drain region and a channel region which is implanted in the substrate beneath the bottom surface of the trench. In one embodiment, the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment, the top surface and a portion of the trenched polysilicon gate are above the substrate surface. In yet another embodiment of the present invention, a layer of tungsten silicide or tungsten film is formed over the top surface of the trenched polysilicon gate. In still yet another embodiment, a layer of tungsten silicide or tungsten film is also formed on the side surfaces of the trenched polysilicon gate.
In accordance with one embodiment of the present invention, an MOS device with a trenched polysilicon gate is fabricated by first etching a trench in the silicon substrate and implanting the substrate with dopant impurities to form a channel region beneath the trench. A trench-to-gate insulating layer is formed in the trench followed by a layer of polysilicon to form the trenched polysilicon gate. In one embodiment, the polysilicon gate layer is planarized until the polysilicon is substantially planar with the substrate surface, and a layer of tungsten silicide is formed on the surface of the trenched polysilicon gate. In another embodiment, the polysilicon layer is patterned and etched to form a trenched polysilicon gate having a portion of the polysilicon above the substrate surface. A layer of tungsten silicide is then formed on the trenched polysilicon gate. In yet another embodiment, the polysilicon gate layer is planarized or patterned with tungsten film as transistor gate interconnects.